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I will be replacing Professor Agarwal today because he is away. I am one of the recitation instructors for those of you who have not seen me. We will talk today about a neat application of RC networks and expand those to application in MOS memory systems.

To connect with everything, we will get back to the basic circuit that we have been discussing so far. And you recall the circuit that we have been studying, the canonical RC with an input voltage function of t.

And we had specified that we solved this problem for the case of a step input or a condition in which a t=0. At t greater or equal to zero vI is equal to some capital VI value that for now on is constant.

And the other condition that we discussed was the value of the voltage on the capacitor that would exist at time t=0. Let's call that vc(0). And in general there is some finite value here. It can be zero or it can be different from zero.

Given that, we learned how to write down directly, without messing around with differential equations, the answer for the voltage on the capacitor vc(t), let me define also my vc right here, is equal to VI, the final value, plus vc(0), the initial value on the capacitor, minus the final value, e^–t/RC.

This is our standard equation to which we plug in, and it's either a rising exponential if VI is larger than VC or a decaying exponential if VI is a smaller value than VC. This should all be familiar.

And, again, as pointed out in the notes, the reading for today is 10.3 and for the new material you should look at Chapter 11 where we discuss memory. This is where we stood as of last time. Now, I would like to discuss a little bit more about the storage of charge in capacitors.

And how we can take advantage of that for storing logic state. One of the things that I am sure you must be aware of is that one of the perhaps most massively produced chips is actually the so-called DRAM which you find in every PC and every computer that exists anywhere.

This DRAM is dynamic random access memory in which we can store a state and come back and look at it at any time later, provided we don't power off our machine. The logic state in the basic memory elements, of which instead there are close to 1 giga elements per chip, are stored on capacitors.

And so we will play a little bit with that concept today. And, although we're not going to discuss the specific example of the DRAM, the basic elements of the DRAM you will see actually in a demo shortly.

So that's the general response of this network that I have here to an input VI that happens at t=0. Now, the one thing that you recognize immediately is that it really doesn't matter what the value of VI was for t less than zero.

What really counts is the value of VI at t=0. And that's the value that we're interested in. Now, there is an implicit statement in that. And that statement is that somehow that network appears like this at t=0.

So, there has to be some switch there, and you will see that, that basically starts my condition to that at t=0. And so the history of VI really doesn't matter. The response following that equation that we have there will depend on the initial value which is vc(0) here.

Now that is the voltage on the capacitor at that time. And then assuming that VI is a value that is larger than vc(0) will have a rising exponential that will come to this value. And this is the time constant RC and this is time.

To connect with everything, we will get back to the basic circuit that we have been discussing so far. And you recall the circuit that we have been studying, the canonical RC with an input voltage function of t.

And we had specified that we solved this problem for the case of a step input or a condition in which a t=0. At t greater or equal to zero vI is equal to some capital VI value that for now on is constant.

And the other condition that we discussed was the value of the voltage on the capacitor that would exist at time t=0. Let's call that vc(0). And in general there is some finite value here. It can be zero or it can be different from zero.

Given that, we learned how to write down directly, without messing around with differential equations, the answer for the voltage on the capacitor vc(t), let me define also my vc right here, is equal to VI, the final value, plus vc(0), the initial value on the capacitor, minus the final value, e^–t/RC.

This is our standard equation to which we plug in, and it's either a rising exponential if VI is larger than VC or a decaying exponential if VI is a smaller value than VC. This should all be familiar.

And, again, as pointed out in the notes, the reading for today is 10.3 and for the new material you should look at Chapter 11 where we discuss memory. This is where we stood as of last time. Now, I would like to discuss a little bit more about the storage of charge in capacitors.

And how we can take advantage of that for storing logic state. One of the things that I am sure you must be aware of is that one of the perhaps most massively produced chips is actually the so-called DRAM which you find in every PC and every computer that exists anywhere.

This DRAM is dynamic random access memory in which we can store a state and come back and look at it at any time later, provided we don't power off our machine. The logic state in the basic memory elements, of which instead there are close to 1 giga elements per chip, are stored on capacitors.

And so we will play a little bit with that concept today. And, although we're not going to discuss the specific example of the DRAM, the basic elements of the DRAM you will see actually in a demo shortly.

So that's the general response of this network that I have here to an input VI that happens at t=0. Now, the one thing that you recognize immediately is that it really doesn't matter what the value of VI was for t less than zero.

What really counts is the value of VI at t=0. And that's the value that we're interested in. Now, there is an implicit statement in that. And that statement is that somehow that network appears like this at t=0.

So, there has to be some switch there, and you will see that, that basically starts my condition to that at t=0. And so the history of VI really doesn't matter. The response following that equation that we have there will depend on the initial value which is vc(0) here.

Now that is the voltage on the capacitor at that time. And then assuming that VI is a value that is larger than vc(0) will have a rising exponential that will come to this value. And this is the time constant RC and this is time.

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